"Computer architects are facing two critical challenges when designingparallel architectures - making them both dramatically more power efficientand far more easy to program. These challenges, often referred to as thepower and programmability walls, already bring forth two orthogonal paradigmshifts in parallel programming and computer architecture.On the one hand, the parallel programming world is turning towardstask-based parallel programming models, which direct programmers todecompose their program into computational tasks that can execute inan asynchronous manner. On the other hand, power limitations andinefficiencies inherent to von-Neumann architectures motivate theexploration of novel programmable accelerators.In this research, whose focus stems from the culmination of the abovetrends, we will focus on the exploration and design ofhigh-performance, power-efficient compute fabric that is tuned toefficient execution of encapsulated computational tasks. To achievehigh-performance as well as power efficiency, the fabric will be basedthe dataflow computing model, which potentially offers great power andperformance potential over traditional von-Neumann architectures.The research will focus on the development of a novel single-graphmultiple-flows (SGMF) reconfigurable accelerator model that combinestask-level parallelism with power-efficient data graph execution. TheSGMF model identifies multiple instances of a computational task typeand maps their shared data graph representation onto a grid of simplefunctional units. The grid then concurrently streams multiple datagraph instances thus executes tasks in parallel. SGMF therefore offersa general-purpose, power-efficient dataflow alternative for theincreasingly popular single-instruction multiple-thread (SIMT) model."