We propose to fabricate a chip implementing a neuromorphic architecture that supports state-of-the-art machine learning algorithms and spike-based learning mechanisms. With respect to its physical architecture this chip will feature an ultra low power, scalable and highly configurable neural architecture that will deliver a gain of a factor 50x in power consumption on selected applications compared to conventional digital solutions; and a monolithically integrated 3D technology in Fully-Depleted Silicon on Insulator (FDSOI) at 28nm design rules with integrated Resistive Random Access Memory (RRAM) synaptic elements;We will complete this vision and develop complementary technologies that will allow to address the full spectrum of applications from mobile/autonomous objects to high performance computing coprocessing, by realising (1) a technology to implement on-chip learning, using native adaptive characteristics of electronic synaptic elements; and (2) a scalable platform to interconnect multiple neuromorphic processor chips to build large neural processing systems.The neuromorphic computing system will be developed jointly with advanced neural algorithmsand computational architectures for online adaptation, learning, and high-throughput on-line signalprocessing, delivering1. an ultra-low power massively parallel non von Neumann computing platform with non-volatile nano-scale devices that support on-line learning mechanisms2. a programming toolbox of algorithms and data structures tailored to the specific constraints and opportunities of the physical architecture;3. an array of fundamental application demonstrations instantiating the basic classes of signal processing tasks.The neural chip will validate the concept and be a first step to develop a European technology platform addressing from ultra-low power data processing in autonomous systems (Internet of Things) to energy efficient large data processing in servers and networks.