The semiconductor industry is a cornerstone of today's high-tech economy, supporting over 100,000 direct and even more indirect jobs in Europe. This position has been achieved through continued miniaturization in complementary metal-oxide-semiconductor (CMOS) technology, which will only last for a maximum 10-15 more years. In line with its Lisbon Strategy, the EC has identified an urgent need to assess possible technology solutions for the "Beyond CMOS" era to meet the challenges of global competition.The major ICT challenge is to find alternatives for information processing and storage beyond the limits of existing CMOS. Graphene, ultrathin layers of carbon, is particularly promising due its novel electronic properties. Initial data indicates that graphene is a prime candidate for "Beyond CMOS" switches and interconnects, and is, despite its revolutionary nature, complementary to conventional CMOS.The key objective of the GRAND proposal is to verify and assess whether graphene can bring conventional semiconductor technology to the "Beyond CMOS" era. GRAND is thus positioned to act as a pathfinder for key ICT challenges.The GRAND consortium will develop industry-compatible strategies for fabrication of 2D graphene nanostructures (widths down to the 5 nm scale) for switches and interconnects. Edge states, critical for transport at this scale, will be manipulated by functionalization methods. Device transport properties will be experimentally evaluated, complemented by a range of modelling techniques including simplified Monte Carlo models to describe scattering and hot phonon effects, as well as atomistic and ab-initio methods for band structure calculations. The consortium includes internationally renowned experimental and theoretical groups from academia and industry, forming a comprehensive unit with capabilities far beyond those of the individual partners, and ensuring a tight focus on the exploitation of the project results for European industry.