The project aims to realise a strong methodology for the development and design of non volatile memories usign standard CMOS silicon process actually used for consumer electronics. Since standard silicon memories, such as other silicon devices for consumer market, fails under irradiation two different approaches are envisaged: the first one is to develop specific technological processes able to substain heavy ions and other charged particles while the second one is more devoted to use specific design and architectures.The first approach, also known as Radiation Hardening by Process (RHBP), is very expensive and tied to technological issues which can be faced only by large corporates and, due to the very low amount of final devices to be realised, very difficult to follow (great deal of effort for a small niche market).The second approach, also known as Radiation Hardening by Design (RHBD), takes the best from standard CMOS consumer processes and, using very accurate design methodologies, mitigates radiation effects on silicon processes.Semiconductor memories, among rad hard integrated circuit scenario, are one of the most critical topic and non volatile memories in particular.Actually both volatile and non volatile memories, excluding few excpetions, are integrated using standard processes and standard architectures. This means that the final device is typically at least Rad Tolerant and not Rad Hard and failure during mission is avoided using Error Correctin Code techniques including redundancy (more devices of the same type are used in voting manner) at board level.The basic goal of the project is to give a methodology for the development of a generic rad hard non volatile memory with the features actually used in consumer market (good retention, reprogrammability and cyclicity) and realise a prototype (1Mbit Flash Memory) in order to validate the approach.