"The current integrated circuit scaling hits two major roadblocks or walls. One wall is the atomic level feature sizes of the current devices forcing the capabilities of even nano-scale implementations. The other wall is the total power consumed per unit area exceeding the capabilities thermal dissipation techniques limiting the maximum device densities. The solution to the feature size problem is scaling in the orthogonal direction to the conventional device plane - the 3D integration. The solution to the power problem is the use of ultra low power design approaches. However, the 3D integration increases the thermal dissipation problem and ultra low power design can not provide total performance due to low clock speeds unless extremely large number of devices is combined in small areas. We propose a unique combination of ultra low power design approaches and 3D integration to provide an optimal performance to the user. Low power design eliminates the thermal dissipation problem of the 3D integration whereas 3D integration enables dense device integration in small volumes to solve the space-time trade-off in ultra low power design approaches. The result will be a vertically integrated circuit with power efficiencies several hundred times better than current dedicated processors."