As miniaturization of the CMOS technology advances designers will have to deal with increased variability and changing performance of devices. Intrinsic variability of devices which begins to be visible in 65nm devices already will become much more significant in smaller technologies. Soon it will not be possible to design systems using current methods and techniques.Scaling beyond the 32 nm technology node brings a number of problems whose impact on design has not been evaluated yet. Random intra-die process variability, reliability degradation mechanisms and their combined impact on the system level parametric quality metrics are becoming prominent issues.Dealing with these new challenges will require an adaptation of the current design process: a combination of design time and runtime techniques and methods will be needed to guarantee the correct functioning of Systems on Chip (SoC) over the product's lifetime, despite the fabrication in unreliable nano-scale technologies.The objective of this project is to develop design techniques and methods for real-time guaranteed, energy-efficient, robust and self-adaptive SoCs.The technological challenges to be tackled are:(a) Increased static variability and static fault rates of devices and interconnects;(b) Increased time-dependent dynamic variability and dynamic fault rates.(c) Build reliable systems out of unreliable technology while maintaining design productivity;(d) Deploy design techniques that allow technology scalable energy efficient SoC systems while guaranteeing real-time performance constraints.In order to tackle these challenges we focus our effort along two main axes:(a) Analysis of the system in terms of performance, power and reliability of manufactured instances across a wide spectrum of operating conditions.(b) Solution techniques to mitigate impact of reliability issues of integrated circuits, at component, circuit, and architecture and system design.