In the semiconductor industry, CMOS technology will certainly continue to have a predominant market position in the future. However, there are still a number of technological challenges, which have to be tackled if CMOS downscaling should be pursued until feature sizes will reach 10 nm around the year 2015-2020.The NanoICT Coordination Action activities will reinforce and support the whole European Research Community in "ICT nanoscale devices" covering the following research areas expected to demonstrate unconventional solutions beyond the expected limits of CMOS technology.• Demonstration of new concepts for switches or memory cells• Demonstration of new concepts, technologies and architectures for local and chip level interconnects with substantial improvements over current solutions• Demonstration of radically new functionalities by the integration of blocks from a few nanometres down to the atomic scale into high added-value systemsThe CA action plans will go beyond the organisation of conferences, workshops, exchange of personnel, WEB site, etc. developing the following activities:• Consolidation and visibility of the research community in ICT nanoscale devices• Mapping and benchmarking of research at European level, and its comparison with other continents• Identification of drivers and measures to assess research in ICT nanoscale devices, and to assess the potential of results to be taken up in industrial research• Coordination of research agendas and development of research roadmaps• Coordination of national or regional research programmes or activities, with the aim to involve funding authorities in building the ERA around this topic• Development of strategies for international cooperation on themes related to NanoICTExpected impact will be the enhanced visibility, shaping and consolidation of the NanoICT research community in Europe.