Fast, high capacity, low form factor and low power non-volatile memories are a crucial enabler of today's ICT. They are already an important part of all electronic systems, representing a growing market segment, and should increase their importance in the future en route towards the "Storage everywhere" society. The market today is divided between Flash NAND and hard disk, which both face severe limitations for the mid term future (2012-2014). The recent discovery that domain walls (DWs) can be moved under a small current without any magnetic field opens a perspective for a paradigm shift in mass storage design. This project aims at demonstrating the disruptive concept of the "storage track memory", which proposes to store information in DW sequences moving synchronously under current in patterned magnetic tracks. It reproduces the successful data sector memory organization of a hard disk in a solid state device with no mechanically moving parts. Our project aims at investigating the potential of a race track storage device beyond the 32nm technology node by proposing innovative solutions in the fields of materials, DW spin structure engineering, fabrication processes, architecture and CMOS integration. Our ultimate goal is to implement the integrated race track memory device in the standard CMOS 45nm technology node to fully benefit from the cost/scalability economics reflected by Moore's law.In the EU, pioneering work has been done and key expertise is available but scattered in different academic laboratories of different countries. This project gathers four leading academic experts, a major semiconductor manufacturer and a PVD equipment manufacturer for the Magnetic Storage Market. This project is expected to generate a strong impact in terms of European IPR and mass-storage applications beyond the limits of NAND Flash technology. It will be an essential step in the development of all future ICT applications and in particular for mobile devices.