The ongoing miniaturization of data processing and storage devices and the imperative of low-energy consumption can only be sustained through low-powered components. Lower supply voltages and variations in technological process of emerging nanoelectronic devices make them inherently unreliable. As a consequence, the nanoscale integration of chips built out of unreliable components has emerged as one of the most critical challenges for the next-generation electronic circuit design. To make such nanoscale integration economically viable, new solutions for efficient and fault-tolerant data processing and storage must now be invented. The i-RISC project aims at achieving these goals, by providing innovative fault-tolerant solutions at both device- and system-level that are fundamentally rooted in mathematical models, algorithms, and techniques of information theory. Proposed solutions will build on error correcting codes and encoder/decoder architectures able to provide reliable error protection even if they themselves operate on unreliable hardware. The project will develop the scientific foundation and provide a first proof-of-concept by validating the proposed solutions on accurate error models and energy measurement tools developed within the project. In the forthcoming challenge of nanoscale technologies, the i-RISC project is an essential prerequisite for preparing the European industry for this paradigm shift.